1. Field of the Invention
The present invention relates to the field of data processing systems. More particularly, this invention relates to a data processing system in which it is desired to provide single instruction multiple data (SIMD) type operation.
2. Description of the Prior Art
Single instruction multiple data (SIMD) operation is a known technique whereby data words being manipulated in accordance with a single instruction in fact represent multiple data values within those data words with the manipulation specified being independently performed upon respective data values. This type of instruction can increase the efficiency with which a data processing system operates and is particularly useful in reducing code size and speeding up processing operation. The technique is commonly, but not exclusively, applied to the field of manipulating data values representing physical signals, such as in digital signal processing applications. A drawback of this approach is that the operations take place in parallel on independent data-sets, and that special provisions must be made to combine those data-sets, thereby reducing the efficiency, and increasing the complexity.
An alternative method to increase the parallel computation capability is simply by adding more functional units to perform the computations. Yet, when extending the data processing capabilities of a data processing system, an important consideration is the extent of any size, complexity, cost and power consumption overheads that may be introduced to support the additional processing capabilities. Although it is desirable to achieve a high effective level of instruction execution parallelism in data processing systems, the need for many additional control bits to control movement of data between a data store (such as a register file) and data processing logic can be detrimental to the efficiency of the data processor. Constraints can be imposed on data movements to and from data storage locations to counter the increase in control complexity. However, these constraints have adverse effects on both compiler and effective computational performance that typically offset the advantages theoretically achievable by introducing the instruction execution parallelism.